The present invention relates to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch.
Field effect transistors (FETs) are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
FinFETs are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 22 nm node. FinFET structures include at least one narrow semiconductor fin as the channel region of the FET and are gated on at least two sides of each of the at least one semiconductor fin. FinFETs including more than one fin may be referred to as multi-fin FinFETs. FinFET structures may be formed on a semiconductor-on-insulator (SOI) substrate because of the low source/drain diffusion, low substrate capacitance, and ease of electrical isolation by STI structures. FinFETs may be also formed on bulk substrates to reduce wafer cost and/or enable formation of certain devices in the bulk substrate.